| Part Number(s) (NSID) |
Top View | Type | Pins | MSL Rating | Peak Reflow | RoHS Status |
CAD Symbols | Models | Package Marking Format |
|---|---|---|---|---|---|---|---|---|---|
| LP2995LQ/NOPB LP2995LQ |
LLP | 16 | 3 1 |
260 235 |
Detail | Download | N/A |
NS UZXYTT L00005B |
|
| LP2995M/NOPB LP2995M |
 |
SOIC NARROW | 8 | 1 1 |
260 235 |
Detail | Download | N/A |
NSZXTT 2995M |
| LP2995MR/NOPB LP2995MR |
 |
PSOP | 8 | 3 3 |
260 260 |
Detail | Download | N/A |
NSXYTT LP2995 |
| LP2995MRX/NOPB LP2995MRX |
|
PSOP | 8 | 3 3 |
260 260 |
Detail | Download | N/A |
NSXYTT LP2995 |
| LP2995MX/NOPB LP2995MX |
|
SOIC NARROW | 8 | 1 1 |
260 235 |
Detail | Download | N/A |
NSZXTT 2995M |
Description
The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.
Patents Pending
| • | DDR Termination Voltage |
| • | SSTL-2 |
| • | SSTL-3 |
| • | Low output voltage offset |
| • | Works with +5v, +3.3v and 2.5v rails |
| • | Source and sink current |
| • | Low external component count |
| • | No external resistors required |
| • | Linear topology |
| • | Available in SO-8, PSOP-8 or LLP-16 packages |
| • | Low cost and easy to use |
Diagrams
Typical Application
|
Block Diagram
|
Typical Performance  source：ShenZhen henlito electronic co.,ltd.
web:www.henlito.com |
