Pricing / Packaging
| Device | Status | Temp (oC) | Price | Quantity | Package | Pins | Package QTY | Package Carrier |
| 74ABT16823DGGRE4 | ACTIVE | -40 to 85 | 2.31 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R |
| 74ABT16823DGGRG4 | ACTIVE | -40 to 85 | 2.31 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R |
| SN74ABT16823DGGR | ACTIVE | -40 to 85 | 2.31 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R |
| SN74ABT16823DGVR | ACTIVE | -40 to 85 | 1.90 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R |
| SN74ABT16823DGVRE4 | ACTIVE | -40 to 85 | 1.90 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R |
| SN74ABT16823DGVRG4 | ACTIVE | -40 to 85 | 1.90 | 1ku | TVSOP (DGV) | 56 | 2000 | LARGE T&R |
| SN74ABT16823DL | ACTIVE | -40 to 85 | 2.30 | 1ku | SSOP (DL) | 56 | 20 | TUBE |
| SN74ABT16823DLG4 | ACTIVE | -40 to 85 | 2.30 | 1ku | SSOP (DL) | 56 | 20 | TUBE |
| SN74ABT16823DLR | ACTIVE | -40 to 85 | 2.31 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R |
| SN74ABT16823DLRG4 | ACTIVE | -40 to 85 | 2.31 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R |
Description
These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (
) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking high disables the clock buffer, latching the outputs. Taking the clear (
) input low causes the Q outputs to go low independently of the clock.
A buffered output-enable (
) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state.
Features
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- High-Impedance State During Power Up and Power Down
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
source：ShenZhen henlito electronic co.,ltd.
web:www.henlito.com
