SN74CBTLV3125D Low-Voltage Quadruple FET Bus Switch

Pricing / Packaging

Device	Status	Temp (oC)	Price | Quantity	Package| Pins	Top Side Marking
74CBTLV3125DBQRE4	ACTIVE	-40 to 85	0.48 | 1ku	SSOP/QSOP (DBQ)| 16	View
74CBTLV3125DBQRG4	ACTIVE	-40 to 85	0.48 | 1ku	SSOP/QSOP (DBQ)| 16	View
74CBTLV3125DGVRE4	ACTIVE	-40 to 85	0.48 | 1ku	TVSOP (DGV)| 14
74CBTLV3125DGVRG4	ACTIVE	-40 to 85	0.48 | 1ku	TVSOP (DGV)| 14
74CBTLV3125NSRG4	ACTIVE	-40 to 85	0.48 | 1ku	SO (NS)| 14	View
74CBTLV3125PWRE4	ACTIVE	-40 to 85	0.48 | 1ku	TSSOP (PW)| 14	View
74CBTLV3125PWRG4	ACTIVE	-40 to 85	0.48 | 1ku	TSSOP (PW)| 14	View
74CBTLV3125RGYRG4	ACTIVE	-40 to 85	0.59 | 1ku	VQFN (RGY)| 14	View
SN74CBTLV3125D	ACTIVE	-40 to 85	0.60 | 1ku	SOIC (D)| 14	View
SN74CBTLV3125DBQR	ACTIVE	-40 to 85	0.48 | 1ku	SSOP/QSOP (DBQ)| 16	View
SN74CBTLV3125DE4	ACTIVE	-40 to 85	0.60 | 1ku	SOIC (D)| 14	View
SN74CBTLV3125DG4	ACTIVE	-40 to 85	0.60 | 1ku	SOIC (D)| 14	View
SN74CBTLV3125DGVR	ACTIVE	-40 to 85	0.48 | 1ku	TVSOP (DGV)| 14
SN74CBTLV3125DR	ACTIVE	-40 to 85	0.48 | 1ku	SOIC (D)| 14	View
SN74CBTLV3125DRE4	ACTIVE	-40 to 85	0.48 | 1ku	SOIC (D)| 14	View
SN74CBTLV3125DRG4	ACTIVE	-40 to 85	0.48 | 1ku	SOIC (D)| 14	View
SN74CBTLV3125NSR	ACTIVE	-40 to 85	0.48 | 1ku	SO (NS)| 14	View
SN74CBTLV3125NSRE4	ACTIVE	-40 to 85	0.48 | 1ku	SO (NS)| 14	View
SN74CBTLV3125PW	ACTIVE	-40 to 85	0.60 | 1ku	TSSOP (PW)| 14	View
SN74CBTLV3125PWE4	ACTIVE	-40 to 85	0.60 | 1ku	TSSOP (PW)| 14	View
SN74CBTLV3125PWG4	ACTIVE	-40 to 85	0.60 | 1ku	TSSOP (PW)| 14	View
SN74CBTLV3125PWR	ACTIVE	-40 to 85	0.48 | 1ku	TSSOP (PW)| 14	View
SN74CBTLV3125RGYR	ACTIVE	-40 to 85	0.59 | 1ku	VQFN (RGY)| 14	View

Description

The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE\) input is high.

This device is fully specified for partial-power-down applications using I_off. The I_off feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

• Standard ¡¯125-Type Pinout
• 5- Switch Connection Between Two Ports
• Rail-to-Rail Switching on Data I/O Ports
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

source£ºShenZhen henlito electronic co.,ltd.

web:www.henlito.com