Pricing / Packaging
| Device | Status | Temp (oC) | Price | Quantity | Package | Pins | Top Side Marking | Package QTY | Package Carrier |
| SN74ABT823DBLE | OBSOLETE | -40 to 85 | SSOP (DB) | 24 | View | ||
| SN74ABT823DBR | ACTIVE | -40 to 85 | 1.28 | 1ku | SSOP (DB) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823DBRG4 | ACTIVE | -40 to 85 | 1.28 | 1ku | SSOP (DB) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823DW | ACTIVE | -40 to 85 | 1.30 | 1ku | SOIC (DW) | 24 | View | 25 | TUBE |
| SN74ABT823DWE4 | ACTIVE | -40 to 85 | 1.30 | 1ku | SOIC (DW) | 24 | View | 25 | TUBE |
| SN74ABT823DWG4 | ACTIVE | -40 to 85 | 1.30 | 1ku | SOIC (DW) | 24 | View | 25 | TUBE |
| SN74ABT823DWR | ACTIVE | -40 to 85 | 1.28 | 1ku | SOIC (DW) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823DWRE4 | ACTIVE | -40 to 85 | 1.28 | 1ku | SOIC (DW) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823DWRG4 | ACTIVE | -40 to 85 | 1.28 | 1ku | SOIC (DW) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823NSR | ACTIVE | -40 to 85 | 1.28 | 1ku | SO (NS) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823NSRE4 | ACTIVE | -40 to 85 | 1.28 | 1ku | SO (NS) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823NSRG4 | ACTIVE | -40 to 85 | 1.28 | 1ku | SO (NS) | 24 | View | 2000 | LARGE T&R |
| SN74ABT823NT | ACTIVE | -40 to 85 | 1.28 | 1ku | PDIP (NT) | 24 | 15 | TUBE | |
| SN74ABT823NTE4 | ACTIVE | -40 to 85 | 1.28 | 1ku | PDIP (NT) | 24 | 15 | TUBE |
Description
These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
With the clock-enable (CLKEN\) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR\) input low causes the nine Q outputs to go low, independently of the clock.
A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state.
Features
- State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- High-Impedance State During Power Up and Power Down
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Buffered Control Inputs to Reduce dc Loading Effects
- Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (NT) and Ceramic (JT) DIPs
EPIC-IIB is a trademark of Texas Instruments Incorporated.
source：ShenZhen henlito electronic co.,ltd.
web:www.henlito.com
