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SN74ABT125DR Quadruple Bus Buffer Gates With 3-State Outputs


source: | post time:2010-01-22

Pricing / Packaging

Device Status Temp (oC) Price | Quantity Package | Pins Package QTY | Package Carrier
SN74ABT125D ACTIVE -40 to 85 0.36 | 1ku SOIC (D) | 14 50 | TUBE Download CAD Format for this Footprint
SN74ABT125DBLE OBSOLETE -40 to 85   SSOP (DB) | 14   Download CAD Format for this Footprint
SN74ABT125DBR ACTIVE -40 to 85 0.35 | 1ku SSOP (DB) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125DBRE4 ACTIVE -40 to 85 0.35 | 1ku SSOP (DB) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125DBRG4 ACTIVE -40 to 85 0.35 | 1ku SSOP (DB) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125DE4 ACTIVE -40 to 85 0.36 | 1ku SOIC (D) | 14 50 | TUBE Download CAD Format for this Footprint
SN74ABT125DG4 ACTIVE -40 to 85 0.36 | 1ku SOIC (D) | 14 50 | TUBE Download CAD Format for this Footprint
SN74ABT125DR ACTIVE -40 to 85 0.35 | 1ku SOIC (D) | 14 2500 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125DRE4 ACTIVE -40 to 85 0.35 | 1ku SOIC (D) | 14 2500 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125DRG4 ACTIVE -40 to 85 0.35 | 1ku SOIC (D) | 14 2500 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125N ACTIVE -40 to 85 0.35 | 1ku PDIP (N) | 14 25 | TUBE Download CAD Format for this Footprint
SN74ABT125NE4 ACTIVE -40 to 85 0.35 | 1ku PDIP (N) | 14 25 | TUBE Download CAD Format for this Footprint
SN74ABT125NSR ACTIVE -40 to 85 0.35 | 1ku SO (NS) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125NSRE4 ACTIVE -40 to 85 0.35 | 1ku SO (NS) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125NSRG4 ACTIVE -40 to 85 0.35 | 1ku SO (NS) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125PW ACTIVE -40 to 85 0.39 | 1ku TSSOP (PW) | 14 90 | TUBE Download CAD Format for this Footprint
SN74ABT125PWE4 ACTIVE -40 to 85 0.39 | 1ku TSSOP (PW) | 14 90 | TUBE Download CAD Format for this Footprint
SN74ABT125PWG4 ACTIVE -40 to 85 0.39 | 1ku TSSOP (PW) | 14 90 | TUBE Download CAD Format for this Footprint
SN74ABT125PWLE OBSOLETE -40 to 85   TSSOP (PW) | 14   Download CAD Format for this Footprint
SN74ABT125PWR ACTIVE -40 to 85 0.39 | 1ku TSSOP (PW) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125PWRE4 ACTIVE -40 to 85 0.39 | 1ku TSSOP (PW) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125PWRG4 ACTIVE -40 to 85 0.39 | 1ku TSSOP (PW) | 14 2000 | LARGE T&R Download CAD Format for this Footprint
SN74ABT125RGYR ACTIVE -40 to 85 0.44 | 1ku VQFN (RGY) | 14 3000 | LARGE T&R
SN74ABT125RGYRG4 ACTIVE -40 to 85 0.44 | 1ku VQFN (RGY) | 14 3000 | LARGE T&R
Description

The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

 Typical VOLP (Output Ground Bounce)
   <1 V at VCC = 5 V, TA = 25°C

  • High-Drive Outputs (–32-mA IOH, 64-mA IOL)
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

source:ShenZhen henlito electronic co.,ltd.

web:www.henlito.com


Prev:SN74ABT823DBR 9-Bit Bus-Interface Flip-Flops With 3-State Outputs
Next:SN74ABT162244DGGR 16-Bit Buffers/Drivers With 3-State Outputs


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