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TL16C752BPTG4 Dual UART With 64-Byte FIFO


source: | post time:2010-02-16

Pricing / Packaging

Device Status Temp (oC) Price | Quantity Package| Pins Top Side Marking Package QTY| Package Carrier
TL16C752BPT ACTIVE -40 to 85 2.90 | 1ku LQFP (PT)| 48 View 250 | JEDEC TRAY (10+1) Download CAD Format for this Symbol Download CAD Format for this Footprint
TL16C752BPTG4 ACTIVE -40 to 85 2.90 | 1ku LQFP (PT)| 48 View 250 | JEDEC TRAY (10+1) Download CAD Format for this Symbol Download CAD Format for this Footprint
TL16C752BPTR ACTIVE -40 to 85 2.60 | 1ku LQFP (PT)| 48 View 1000 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this Footprint
TL16C752BPTRG4 ACTIVE -40 to 85 2.60 | 1ku LQFP (PT)| 48 View 1000 | LARGE T&R Download CAD Format for this Symbol Download CAD Format for this Footprint

Description

The TL16C752B is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps. The TL16C752B offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal.

Features

  • Pin Compatible With ST16C2550 With Additional Enhancements
  • Up to 1.5 Mbps Baud Rate When Using Crystal (24 MHz Input Clock)
  • Up to 3 Mbps Baud Rate When Using Oscillator or Clock Source (48 MHz Input Clock)
  • 64-Byte Transmit FIFO
  • 64-Byte Receive FIFO With Error Flags
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation
  • Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon/Xoff Characters
    • Programmable Auto- RTS\ and Auto- CTS\
  • Optional Data Flow Resume by Xon Any Character
  • DMA Signalling Capability for Both Received and Transmitted Data
  • Supports 3.3-V Operation
  • Software Selectable Baud Rate Generator
  • Prescaler Provides Additional Divide By 4 Function
  • Fast Access Time 2 Clock Cycle IOR\/ IOW\ Pulse Width
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5, 6, 7, or 8 Bit Characters
    • Even, Odd, or No Parity Bit Generation and Detection

 

source:ShenZhen henlito electronic co.,ltd.

web:www.henlito.com


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