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ADC08D500 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter from the PowerWise® Family


source: | post time:2010-05-13

Part Number(s)
(NSID)
Top View Type Pins MSL Rating Peak Reflow RoHS
Status
CAD Symbols Models Package
Marking
Format
ADC08D500CIYB/NOPB
ADC08D500CIYB
LQFP EXP PAD 128 3
3
260
260
Detail Download
adc08d500.ibs
NSUZXYYTTE#
ADC08D500
CIYB

PDFClick link to Download

Description

The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 800 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10 -18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C TA +85°C) temperature range.

Key Specification

Resolution

8 Bits

Max Conversion Rate

500 MSPS (min)

Bit Error Rate

10 -18 (typ)

ENOB @ 250 MHz Input

7.5 Bits (typ)

DNL

±0.15 LSB (typ)

Power Consumption

 

Operating

1.4 W (typ)

Power Down Mode

3.5 mW (typ)

Applications

Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation

Features
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock

Diagrams

 

 

 

Block Diagram
*click for larger image


 


Typical Performance
*click for larger image


 


Prev:ADC08D1520 Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter from the PowerWise® Family
Next:ADC10D1000 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS A/D Converter from the PowerWise® Family


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