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ADC10D1000 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS A/D Converter from the PowerWise® Family


source: | post time:2010-05-13

Part Number(s)
(NSID)
Top View Type Pins MSL Rating Peak Reflow RoHS
Status
CAD Symbols Models Package
Marking
Format
ADC10D1000CIUT/NOPB
ADC10D1000CIUT
TEPBGA 292 3
3
250
220
Detail Download
adc10d1000.ibs
NSUZXYYTTE#
ADC10D1000
CIUT

PDFClick link to Download

Description

The ADC10D1000/1500 is the latest advance in National's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10 -18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is guaranteed to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

Key Specification

(Non-Demux Non-DES Mode, Fs=1.0/1.5 GSPS, Fin = 100 MHz)

Resolution

10 Bits

 

  • Conversion Rate

    Dual channels at 1.0/1.5 GSPS (typ)

    Single channel at 2.0/3.0 GSPS (typ)

    Code Error Rate

    10 -18/10 -18 (typ)

    ENOB

    9.1/9.0 bits (typ)

    SNR

    57/56.8 dB (typ)

    SFDR

    70/68 dBc (typ)

    Full Power Bandwidth

    2.8/3.1 GHz (typ)

    DNL

    ±0.25/±0.25 LSB (typ)

     

  • Power Consumption

    Single Channel Enabled

    1.61/1.92W (typ)

    Dual Channels Enabled

    2.77/3.59W (typ)

    Power Down Mode

    6/6 mW (typ)

    Applications

    Wideband Communications
    Data Acquisition Systems
    Digital Oscillosopes

    Diagrams

  • Typical Application
    *click for larger image

    AutoSync diagram

     

     

     

    Block Diagram
    click for larger image

    Block Diagram

     


    Typical Performance
    *click for larger image

    ENOB vs INPUT FREQUENCY

     


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